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products and specifications discussed herein are subject to change by micron without notice. 09005aef807455eb dd8c32_64x32ug_d.fm - rev. d 9/03 en 1 ?2003 micron technology, inc. all rights reserved. 128mb, 256mb (x32, dr) 100-pin ddr dimm ddr sdram dimm module mt8vddt3232u ? 128mb mt8vddt6432u ? 256mb for the latest data sheet, please refer to the micron web site: www.micron.com/moduleds features ? 100-pin, dual in-line memory module (dimm) fast data transfer rate: pc2100 and pc2700 utilizes 266 mt/s or 333 mt/s ddr sdram components 128mb (32 meg x 32) and 256mb (64 meg x 32) v dd = +2.5v 2.5v i/o (sstl_2 compatible) commands entered on each positive ck edge dqs edge-aligned with data for reads; center- aligned with data for writes internal, pipelined double data rate (ddr) architecture; two data accesses per clock cycle bidirectional data strobe (dqs) transmitted/ received with data? i.e. , source-synchronous data capture differential clock inputs ck and ck# four internal device banks for concurrent operation programmable burst lengths: 2, 4, or 8 auto precharge option serial presence detect (spd) with eeprom programmable read cas latency auto refresh and self refresh modes 15.625s (128mb), 7.8125s (256mb) maximum average periodic refresh interval gold edge contacts figure 1: 100-pin dimm (mo-161) note: 1. conact micron for availability of lead-free prod- ucts. 2. cl = cas (read) latency. 3. contact micron for availability of -75e and -75z products. options marking package 100-pin dimm (standard) g 100-pin dimm (lead-free) 1 y frequency/cas latency 2 6ns/167 mhz (333mt/s) cl = 2.5 -6 7.5ns/133 mhz (266 mt/s) cl = 2 -75e 3 7.5ns/133 mhz (266 mt/s) cl = 2 -75z 3 7.5ns/133 mhz (266 mt/s) cl = 2.5 -75 table 1: address table mt8vddt3232u mt8vddt6432u refresh count 4k 8k row addressing 4k (a0?a11) 8k (a0?a12) device bank addressing 4 (ba0, ba1) 4 (ba0, ba1) device configuration 16 meg x 8 32 meg x 8 column addressing 1k (a0?a9) 1k (a0?a9) module rank addressing 2 (s0#, s1#) 2 (s0#, s1#)
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 2 ?2003 micron technology, inc. all rights reserved. table 2: part numbers and timing parameters part number module density configuration module bandwidth memory clock/ data bit rate latency (cl - t rcd - t rp) mt8vddt3232ug-6__ 128mb 32 meg x 32 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt8vddt3232uy-6__ 128mb 32 meg x 32 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt8vddt3232ug-75e__ 128mb 32 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt8vddt3232uy-75e__ 128mb 32 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt8vddt3232ug-75z__ 128mb 32 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt8vddt3232uy-75z__ 128mb 32 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt8vddt3232ug-75__ 128mb 32 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt8vddt3232uy-75__ 128mb 32 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt8vddt6432ug-6__ 256mb 64 meg x 32 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt8vddt6432uy-6__ 256mb 64 meg x 32 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt8vddt6432ug-75e__ 256mb 64 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt8vddt6432uy-75e__ 256mb 64 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2-2-2 mt8vddt6432ug-75z__ 256mb 64 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt8vddt6432uy-75z__ 256mb 64 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt8vddt6432ug-75__ 256mb 64 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt8vddt6432uy-75__ 256mb 64 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 note: all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult factory for current revision codes. example: mt8vddt3232ug-75b1 .
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 3 ?2003 micron technology, inc. all rights reserved. note: pin 21 is no connect for the 128mb module, or a12 for the 256mb module. figure 2: module layout table 3: pin assignment (100-pin dimm front) pin symbol pin symbol pin symbol pin symbol 1dq0 14 v dd 26 a5 39 dq18 2v ss 15 dq11 27 a3 40 dq19 3dq1 16 v ss 28 a1 41 v dd 4dqs017ck0 29 a10 42 dq24 5v dd 18 ck0# 30 v dd 43 dq25 6dq2 19 v dd 31 ba0 44 v ss 7dq3 20 cke1 32 we# 45 dqs3 8v dd 21 nc/ a12 33 s0# 46 dq26 9dq8 22 nc 34 dq16 47 v ss 10 dq9 23 a9 35 v ss 48 dq27 11 v ss 24 a7 36 dq17 49 sa0 12 dqs1 25 v ss 37 dqs2 50 v ref 13 dq10 38 v dd table 4: pin assignment (100-pin dimm back) pin symbol pin symbol pin symbol pin symbol 51 dq4 64 v dd 76 a2 89 dq22 52 v ss 65 dq15 77 a0 90 dq23 53 dq5 66 v ss 78 ba1 91 v dd 54 dm0 67 ck1 79 ras# 92 dq28 55 v dd 68 ck1# 80 v dd 93 dq29 56 dq6 69 v dd 81 cas# 94 v ss 57 dq7 70 cke0 82 s1# 95 dm3 58 v dd 71 a11 83 dnu 96 dq30 59 dq12 72 a8 84 dq20 97 v ss 60 dq13 73 a6 85 v ss 98 dq31 61 v ss 74 a4 86 dq21 99 sda 62 dm1 75 v ss 87 dm2 100 scl 63 dq14 88 v dd u1 u2 u3 u4 u5 u6 u7 u8 u9 pin100 pin 50 pin 23 pin 1 pin 51 pin 73 indicates a v dd or v ddq pin indicates a v ss pin front view back view
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 4 ?2003 micron technology, inc. all rights reserved. table 5: pin descriptions pin numbers may not correlate with symbols. refer to pin assignment tables for pin number and symbol information pin numbers symbol type description 32, 79, 81 we#, cas#, ras# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. 17, 18, 67, 68 ck0, ck0#, ck1, ck1# input clock: ck, ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck,and negative edge of ck#. output data (dq and dqs) is referenced to the crossings of ck and ck#. 20, 70 cke0, cke1 input clock enable: cke high activates and cke low deactivates the internal clock, input buffers and output drivers. taking cke low provides precharge power-down and self refresh operations (all device banks idle), or active power- down (row active in any device bank).cke is synchronous for power-down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit and for disabling the outputs. cke must be maintained high throughout read and write accesses. input buffers (excluding ck, ck#, and cke) are disabled during power-down. input buffers (excluding cke) are disabled during self refresh. cke is an sstl_2 input but will detect an lvcmos low level after v dd is applied and until cke is first brought high. after cke is brought high, it becomes an sstl_2 input only. 33, 82 s0#, s1# input chip selects: s# enables (registered low) and disables (registered high) the command decoder. all commands are masked when s# is registered high. s# is considered part of the command code. 31, 78 ba0, ba1 input bank address: ba0 and ba1 define to which device bank an active, read, write, or precharge command is being applied. 21 (256mb) , 23, 24, 26-29, 71-74, 76, 77 a0?a11 (128mb) a0?a12 (256mb) input address inputs: provide the row address for active commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective device bank. a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low, device bank selected by ba0, ba1) or all device banks (a10 high). the address inputs also provide the op-code during a mode register set command. ba0 and ba1 define which mode register (mode register or extended mode register) is loaded during the load mode register command. 4, 12, 37, 45 dqs0?dqs3 input/ output data strobe: output with read data, input with write data. dqs is edge-aligned with read data, centered in write data. used to capture data. 54, 62, 87, 95 dm0?dm3 input data write mask. dm low allows write operation. dm high blocks write operation. dm lines do not affect read operation. 1, 3, 6, 7, 9,10, 13, 15, 34, 36, 39, 40, 42, 43, 46, 48, 51, 53, 56, 57, 59, 60, 63, 65, 84, 86, 89, 90, 92, 93, 96, 98 dq0?dq31 input/ output data i/os: data bus. 49 sa0 input presence-detect address inputs: these pins are used to configure the presence-detect device.
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 5 ?2003 micron technology, inc. all rights reserved. 99 sda input/ output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and out of the presence- detect portion of the module. 100 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module. 50 v ref input sstl_2 reference voltage. 5, 8, 14, 19, 30, 38, 41, 55, 58, 64, 69, 80, 88, 91 v dd supply power supply: +2.5v 0.2v. 2, 11, 16, 25, 35, 44, 47, 52, 61, 66, 75, 85, 94, 97 v ss supply ground. 83 dnu ? do not use: this pin is not co nnected on these modules, but is an assigned pin on other modules in this product family. 21 (128mb), 22 nc ? no connect: these pins should be left unconnected. table 5: pin descriptions (continued) pin numbers may not correlate with symbols. refer to pin assignment tables for pin number and symbol information pin numbers symbol type description
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 6 ?2003 micron technology, inc. all rights reserved. figure 3: functional block diagram a0 sa0 spd u5 sda a1 a2 ras# cas# cke0 ras#: ddr sdrams cas#: ddr sdrams cke0: ddr sdrams u1-u4 cke1: ddr sdrams u5-u8 we#: ddr sdrams a0-a11: ddr sdrams a0-a12: ddr sdrams ba0: ddr sdrams ba1: ddr sdrams cke1 we# a0-a11 (128mb) a0-a12 (256mb) ba0 ba1 v dd v dd spd ddr sdrams scl s0# s1# u9 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u4 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm cs# dqs u1 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm0 u3 dm cs# dqs dm cs# dqs dm cs# dqs dqs0 dm1 dqs1 dm2 dqs2 dm cs# dqs u8 dm cs# dqs dm cs# dqs dm cs# dqs dm3 dqs3 dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq ddr sdram x 4 ck0 ck0# 120 ddr sdram x 4 ck1 ck1# 120 wp v ss v ref ddr sdrams ddr sdrams, spd u6 dq dq dq dq dq dq dq dq u7 note: all resistor values are 22 unless otherwise specified. per industry standard, micron modules utilize various component speed grades, as referenced in the module part number guide at www.micron.com/numberguide . ddr sdrams = mt46v16m8tg for 128mb module ddr sdrams = mt46v32m8tg for 256mb module
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 7 ?2003 micron technology, inc. all rights reserved. general description the mt8vddt3232u and mt8vddt6432u are high-speed cmos, dynamic random-access, 128mb and 256mb memory modules organized in x32 config- uration. ddr sdram modules use internally config- ured quad-bank ddr sdram devices. ddr sdram modules use a double data rate archi- tecture to achieve high-speed operation. the double data rate architecture is essentially a 2 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr sdram module effec- tively consists of a single 2 n -bit wide, one-clock-cycle data transfer at the internal dram core and two corre- sponding n -bit wide, one-half-clock-cycle data trans- fers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is an intermittent strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. ddr sdram modules operate from differential clock inputs (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and out- put data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to ddr sdram modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the device bank and row to be accessed (ba0, ba1 select devices bank; a0?a11 select device row for 128mb module, a0?a12 select device row for 256mb module). the address bits registered coincident with the read or write command are used to select the device bank and the starting device column location for the burst access (ba0, ba1; a0? a9). ddr sdram modules provide for programmable read or write burst lengths of 2, 4, or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. the pipelined, multibank architecture of ddr sdram modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided, along with a power-saving power-down mode. all inputs are com- patible with the jedec standard for sstl_2. all out- puts are sstl_2, class ii compatible. for more information regarding ddr sdram operation, refer to the 128mb and 256mb ddr sdram component data sheets. serial presence-detect operation ddr sdram modules incorporate serial presence- detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be pro- grammed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, together with sa (2:0), which provide eight unique dimm/eeprom addresses. write protect (wp) is tied to ground on the module, permanently disabling hard- ware write protect. mode register definition the mode register is used to define the specific mode of operation of the ddr sdram. this definition includes the selection of a burst length, a burst type, a cas latency and an operating mode, as shown in figure 4, mode register definition diagram, on page 8. the mode register is programmed via the mode reg- ister set command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is pro- grammed again or the device loses power (except for bit a8, which is self-clearing). reprogramming the mode register will not alter the contents of the memory, provided it is performed cor- rectly. the mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. vio- lating either of these requirements will result in unspecified operation.
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 8 ?2003 micron technology, inc. all rights reserved. mode register bits a0?a2 specify the burst length, a3 specifies the type of burst (sequential or inter- leaved), a4?a6 specify the cas latency, and a7?a11 (128mb) or a7?a12 (256mb) specify the operating mode. burst length read and write accesses to ddr sdram devices are burst oriented, with the burst length being program- mable, as shown in mode register diagram. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both the sequential and the inter- leaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1?a9 when the burst length is set to two, by a2?a9 when the burst length is set to four and by a3?a9 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type and the start- ing column address, as shown in table 6, burst definition table, on page 9. read latency the read latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output data. the latency can be set to 2 or 2.5 clocks, as shown in figure 5, cas latency diagram, on page 9. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . the cas latency table indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 4: mode register definition diagram m3 = 0 reserved 2 4 8 reserved reserved reserved reserved m3 = 1 reserved 2 4 8 reserved reserved reserved reserved operating mode normal operation normal operation/reset dll all other states reserved 0 1 - 0 0 - 0 0 - 0 0 - 0 0 - 0 0 - valid valid - 0 1 burst type sequential interleaved cas latency reserved reserved 2 reserved reserved reserved 2.5 reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 976543 8210 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 operating mode a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 * m14 and m13 (ba1 and ba0) must be ?0, 0? to select the base mode register (vs. the extended mode register). m9 m10 m12 m11 burst length cas latency bt 0* 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 976543 8210 operating mode a10 a11 ba0 ba1 10 11 12 13 * m13 and m12 (ba1and ba0) must be ?0, 0? to select the base mode register (vs. the extended mode register). 128mb module address bus 256mb module address bus
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 9 ?2003 micron technology, inc. all rights reserved. note: 1. for a burst length of two, a1?a9 select the two-data- element block; a0 selects the first access within the block. 2. for a burst length of four, a2?a9 select the four-data- element block; a0?a1 select the first access within the block. 3. for a burst length of eight, a3?a9 select the eight- data-element block; a0?a2 select the first access within the block. 4. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. figure 5: cas latency diagram operating mode the normal operating mode is selected by issuing a mode register set command with bits a7?a11 (for 128mb module), or a7?a12 (256mb module) each set to zero, and bits a0-a6 set to the desired values. a dll reset is initiated by issuing a mode register set command with bits a7 and a9?a11 (for 128mb mod- ule), or a7 and a9?a12 (256mb module) each set to zero, bit a8 set to one, and bits a0?a6 set to the desired values. although not required by the micron device, jedec specifications recommend when a load mode register command is issued to reset the dll, it should always be followed by a load mode regis- ter command to select normal operating mode. all other combinations of values for a7?a11, or a7? a12 are reserved for future use and/or test modes. test modes and reserved states should not be used because unknown operation or incompatibility with future ver- sions may result. extended mode register the extended mode register controls functions beyond those controlled by the mode register; these additional functions are dll enable/disable and out- put drive strength. these functions are controlled via the bits shown in figure 6, extended mode register definition diagram. the extended mode register is programmed via the load mode register com- mand to the mode register (with ba0 = 1 and ba1 = 0) table 6: burst definition table burst length starting column address order of accesses within a burst type = sequential type = interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 table 7: cas latency (cl) table allowable operating clock frequency (mhz) speed cl = 2 cl = 2.5 -6 n/a 75 f 167 -75/-75e/-75z 75 f 100 75 f 133 ck ck# command dq dqs cl = 2 read nop nop nop read nop nop nop burst length = 4 in the cases shown shown with nominal t ac, t dqsck, and t dqsq ck ck# command dq dqs cl = 2.5 t0 t1 t2 t2n t3 t3n t0 t1 t2 t2n t3 t3n don?t care transitioning data
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 10 ?2003 micron technology, inc. all rights reserved. and will retain the stored information until it is pro- grammed again or the device loses power. the enabling of the dll should always be followed by a load mode register command to the mode regis- ter (ba0/ba1 both low) to reset the dll. the extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. violating either of these requirements could result in unspecified oper- ation. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation after having disabled the dll for the purpose of debug or evalua- tion. (when the device exits self refresh mode, the dll is enabled automatically.) any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. figure 6: extende d mode register definition diagram note: 1. ba1 and ba0 (e13 and e12 for 128mb, or e14 and e13 for 256mb) must be ?0, 1? to select the extended mode register (vs. the base mode register). 2. the qfc# option is not supported. operating mode normal operation all other states reserved 0 ? 0 ? valid ? 0 1 dll enable disable dll 1 1 0 1 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 e0 0 drive strength normal e1 e0 e1, operating mode a10 a11 ba1 ba0 10 11 12 13 e3 e4 0 ? 0 ? 0 ? 0 ? 0 ? e6 e5 e7 e8 e9 0 ? 0 ? e10 e11 ds dll 1 1 0 1 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 operating mode a10 a11 a12 ba1 ba0 10 11 12 13 14 ds 128mb module 256mb module 0 ? e2 2
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 11 ?2003 micron technology, inc. all rights reserved. commands ta b l e 8 , tr u th ta bl e ? co mm a nd s , a n d ta b l e 9 , truth table ? dm operation, provide a general refer- ence of available commands. for a more detailed description of commands and operations, refer to the 128mb or 256mb ddr sdram component data sheet. note: 1. deselect and nop are functionally interchangeable. 2. ba0?ba1 provide device bank address and a0-a11 (128mb) or a0?a12 (256mb) provide row address. 3. ba0?ba1 provide device bank address; a0?a9 provide column address; a10 high enables the auto precharge feature (nonpersistent), and a10 low disables the auto precharge feature. 4. applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled and for write bursts. 5. a10 low: ba0?ba1 determine which device bank is precha rged. a10 high: all device banks are precharged and ba0? ba1 are ?don?t care.? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 8. ba0?ba1 select either the mode register or the extended mode register (ba0 = 0, ba1 = 0 select the mode register; ba0 = 1, ba1 = 0 select extended mode register; other combinat ions of ba0?ba1 are reserved). a0?a11 (128mb) or a0?a12 (256mb) provide the op-code to be written to the selected mode register. table 8: truth table ? commands cke is high for all commands shown except self refresh name (function) cs# ras# cas# we# addr notes deselect (nop) hx xx x 1 no operation (nop) lh hh x 1 active (select bank and activate row) l l h h bank/row 2 read (select bank and column, and start read burst) l h l h bank/col 3 write (select bank and column, and start write burst) l h l l bank/col 3 burst terminate lh hl x 4 precharge (deactivate row in bank or banks) l l h l code 5 auto refresh or self refresh (enter self refresh mode) ll lh x 6, 7 load mode register ll llop-code 8 table 9: truth table ? dm operation used to mask write data; provided coincident with the corresponding data name (function) dm dqs write enable l valid write inhibit hx
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 12 ?2003 micron technology, inc. all rights reserved. absolute maximum ratings stresses greater than those listed may cause perma- nent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on v dd supply relative to v ss . . . . . . . . . . . . . . . . . . . . . -1v to +3.6v voltage on v ref and inputs relative to v ss . . . . . . . . . . . . . . . . . . . . -1v to +3.6v voltage on i/o pins relative to v ss . . . . . . . . . . . . . . -0.5v to v dd +0.5v operating temperature, t a (ambient) . . . . . . . . . . . . . . . . . . . . .. 0c to +70c storage temperature (plastic) . . . . . . -55c to +150c short circuit output current. . . . . . . . . . . . . . . 50ma table 10: dc electrical characteristics and operating conditions notes: 1?5, 14, 47; notes appear on pages 17?20; 0c t a +70c parameter/condition symbol min max units notes supply voltage v dd 2.3 2.7 v 32 i/o supply voltage v dd 2.3 2.7 v 32, 38 i/o reference voltage v ref 0.49 v dd 0.51 v dd v6, 38 i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v 7, 38 input high (logic 1) voltage v ih (dc) v ref + 0.15 v dd + 0.3 v 25 input low (logic 0) voltage v il (dc) -0.3 v ref - 0.15 v 25 input leakage current any input 0v v in vdd, v ref pin 0v v in 1.35v (all other pins not under test = 0v) command/ address, ras#, cas#, we# i i -16 16 a 46 cke0, cke1, s0#, s1# ck, ck# -8 8 dm -4 4 output leakage current (dqs are disabled; 0v v out v dd ) dq, dqs i oz -10 10 a 46 output levels high current (v out = v dd -0.373v, minimum v ref , minimum v tt ) low current (v out = 0.373v, maximum v ref , maximum v tt ) i oh -16.8 ? ma 33, 34 i ol 16.8 ? ma table 11: ac input operating conditions notes: 1?5, 14, 47; notes appear on pages 17?20; 0c t a +70c; v dd = +2.5v 0.2v parameter/condition symbol min max units notes input high (logic 1) voltage v ih (ac) v ref + 0.310 ? v 12, 25, 35 input low (logic 0) voltage v il (ac) ? v ref - 0.310 v 12, 25, 35 i/o reference voltage v ref (ac) 0.49 v dd 0.51 v dd v6
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 13 ?2003 micron technology, inc. all rights reserved. ta bl e 1 2 : i dd specifications an d conditions ? 128mb ddr sdram components only notes: 1?5, 14, 47; notes appear on pages 17?20; 0c t a +70c; v dd = +2.5v 0.2v max parameter/condition symbol -6 -75e -75z/-75 units notes operating current: one device bank; active-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cyle; address and control inputs changing once every two clock cycles i dd0 a 512 452 432 ma 20, 41 operating current: one device bank; active -read precharge; burst = 2; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd1 a 552 492 492 ma 20, 41 precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd2p b 12 12 12 ma 21, 28, 43 idle standby current: cs# = high; all device banks idle; t ck = t ck min; cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd2f b 180 180 160 ma 44 active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd3p b 100 100 80 ma 21, 28, 43 active standby current: cs# = hi gh; cke = high; one device bank; active-precharge; t rc = t ras (max); t ck = t ck (min); dq, dm anddqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n b 200 200 180 ma 40 operating current: burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r a 572 532 512 ma 20, 41 operating current: burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w a 572 512 472 ma 20 auto refresh current t rc = t refc(min) i dd5 b 1,060 880 880 ma 20, 43 t refc = 15.625s i dd5a b 20 20 20 ma 24, 43 self refresh current: cke 0.2v i dd6 b 12 12 8 ma 9 operating current: four device bank interleaving reads (bl = 4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands i dd7 a 1,432 1,332 1,312 ma 20, 42 note: a - value calculated as one module rank in this operating condition, and all other module ranks in i dd 2p (cke low) mode. b - value calculated reflects all module ranks in this operating condition.
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 14 ?2003 micron technology, inc. all rights reserved. ta bl e 1 3 : i dd specifications an d conditions ? 256mb ddr sdram components only notes: 1?5, 14, 47; notes appear on pages 17?20; 0c t a +70c; v dd = +2.5v 0.2v max parameter/condition symbol -6 -75e -75z/-75 units notes operating current: one device bank; active-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cyle; address and control inputs changing once every two clock cycles i dd0 a 516 516 436 ma 20, 41 operating current: one device bank; active -read precharge; burst = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd1 a 696 656 596 ma 20, 41 precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd2p b 32 32 32 ma 21, 28, 43 idle standby current: cs# = high; all device banks idle; t ck = t ck min; cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd2f b 400 360 320 ma 44 active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd3p b 240 200 200 ma 21, 28, 43 active standby current: cs# = high; cke = high; one device bank; active-precharge; t rc = t ras (max); t ck = t ck (min); dq, dm anddqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n b 480 400 400 ma 40 operating current: burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r a 716 616 616 ma 20, 41 operating current: burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w a 636 556 556 ma 20 auto refresh current t rc = t refc (min) i dd 5 b 2,040 1,880 1,880 ma 20, 43 t refc = 7.8125s i dd5a b 48 48 48 ma 24, 43 self refresh current: cke 0.2v i dd6 b 32 32 32 ma 9 operating current: four device bank interleaving reads (bl = 4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands i dd7 a 1,636 1,416 1,416 ma 20, 42 note: a - value calculated as one module rank in this operating condition, and all other module ranks in i dd 2p (cke low) mode. b - value calculated reflects all module ranks in this operating condition.
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 15 ?2003 micron technology, inc. all rights reserved. table 14: capacitance (all modules) note: 11; notes appear on pages 17?20 parameter symbol min max units input/output capacitance: dq, dqs, dm c io 810 pf input capacitance: command and address c i1 16 24 pf input capacitance: s#; ck/ck#; cke c i2 812 pf table 15: ddr sdram component electrica l characteristics and recommended ac operating conditions notes: 1?5, 12?15, 29, 47; notes appear on pages 17?20; 0c t a +70c; v dd = +2.5v 0.2v ac characteristics -6 -75 -75e/-75z parameter symbol min max min max min max units notes access window of dq from ck/ck# t ac -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck 26 ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck 26 clock cycle time cl= 2.5 t ck (2.5) 6 13 7.5 13 7.5 13 ns 39, 45 cl = 2 t ck (2) 7.5 13 10 13 10 13 ns 39, 45 dq and dm input hold time relative to dqs t dh 0.45 0.5 0.5 ns 23, 27 dq and dm input setup time relative to dqs t ds 0.45 0.5 0.5 ns 23, 27 dq and dm input pulse width (for each input) t dipw 1.75 1.75 1.75 ns 27 access window of dqs from ck/ck# t dqsck -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 ns dqs input high pulse width t dqsh 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.45 0.5 0.5 ns 22, 23 write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 0.2 t ck half clock period t hp t ch, t cl t ch, t cl t ch, t cl ns 30 data-out high-impedance window from ck/ck# t hz +0.70 +0.75 +0.75 ns 16, 36 data-out low-impedance window from ck/ck# t lz -0.7 -0.75 -0.75 ns 16, 37 address and control input hold time (fast slew rate) t ih f 0.75 0.90 0.90 ns 12 address and control input setup time (fast slew rate) t is f 0.75 0.90 0.90 ns 12 address and control input hold time (slow slew rate) t ih s 0.8 1 1 ns 12 address and control input setup time (slow slew rate) t is s 0.8 1 1 ns 12 address and control input pulse width (for each input) t ipw 2.2 2.2 2.2 ns
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 16 ?2003 micron technology, inc. all rights reserved. load mode register command cycle time t mrd 12 15 15 ns dq?dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs t hp - t qhs t hp - t qhs ns 22, 23 data hold skew factor t qhs 0.6 0.75 0.75 ns active to precharge command t ras 42 70,000 40 120,000 40 120,000 ns 31 active to read with auto precharge command t rap 18 20 20 ns active to active/auto refresh command period t rc 60 65 65 ns auto refresh command period t rfc 72 75 75 ns 43 active to read or write delay t rcd 18 20 20 ns precharge command period t rp 18 20 20 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck 36 dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 12 15 15 ns dqs write preamble t wpre 0.25 0.25 0.25 t ck dqs write preamble setup time t wpres 000ns18, 19 dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 17 write recovery time t wr 15 15 15 ns internal write to read command delay t wtr 111 t ck data valid output window na t qh - t dqsq t qh - t dqsq t qh - t dqsq ns 22 refresh to refresh command interval 128mb t refc 140 140.6 140.6 s 21 256mb 70.3 70.3 70.3 s 21 average periodic refresh interval 128mb t refi 15.6 15.6 15.6 s 21 256mb 7.8 7.8 7.8 s 21 terminating voltage delay to v dd t vtd 000ns exit self refresh to non-read command t xsnr 75 75 75 ns exit self refresh to read command t xsrd 200 200 200 t ck table 15: ddr sdram component electrica l characteristics and recommended ac operating conditions (continued) notes: 1?5, 12?15, 29, 47; notes appear on pages 17?20; 0c t a +70c; v dd = +2.5v 0.2v ac characteristics -6 -75 -75e/-75z parameter symbol min max min max min max units notes
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 17 ?2003 micron technology, inc. all rights reserved. notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter speci- fications are guaranteed for the specified ac input levels under normal use conditions. the mini- mum slew rate for the input signals used to test the device is 1v/ns in the range between v il (ac) and v ih (ac). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. v ref is expected to equal v dd /2 of the transmit- ting device and to track variations in the dc level of the same. peak-to-peak noise (non-common mode) on v ref may not exceed 2 percent of the dc value. thus, from v dd /2, v ref is allowed 25mv for dc error and an additional 25mv for ac noise. this measurement is to be taken at the nearest v ref bypass capacitor. 7. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 8. i dd is dependent on output loading and cycle rates. specified values are obtained with mini- mum cycle time at cl = 2 for -75e and -75z, or cl = 2.5 for -6 and -75 with the outputs open. 9. enables on-chip refresh and address counters. 10. i dd specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 11. this parameter is sampled. v dd = +2.5v 0.2v, v ref = vss, f = 100 mhz, t a =25c, v out (dc) = v dd /2, v out (peak to peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 12. for slew rates < 1 v/ns and to 0.5 vns. if the slew rate is < 0.5v/ns, timing must be derated: t is has an additional 50ps per each 100 mv/ns reduction in slew rate from 500mv/ns, while t ih is unaf- fected. if the slew rate exceeds 4.5 v/ns, function- ality is uncertain. for -6, slew rates must be 0.5 v/ns. 13. the ck/ck# input reference level (for timing ref- erenced to ck/ck#) is the point at which ck and ck# cross; the input reference level for signals other than ck/ck# is v ref . 14. inputs are not recognized as valid until v ref stabi- lizes. exception: during the period before v ref stabilizes, cke 0.3 x v dd is recognized as low. 15. the output timing reference level, as measured at the timing reference point indicated in note 3, is v tt . 16. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 17. the intent of the ?don?t care? state after comple- tion of the postamble is that the dqs-driven sig- nal should either be high, low, or high-z and that any signal transition within the input switch- ing region must follow valid input requirements. if dqs transitions high, above dc v ih (min) then it must not transition low, below dc v ih , prior to t dqsh (min). 18. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low ) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 20. min ( t rc or t rfc) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for i dd measurements is the largest multi- ple of t ck that meets the maximum absolute value for t ras. output (v out ) reference point 50 ? v tt 30pf
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 18 ?2003 micron technology, inc. all rights reserved. 21. the refresh period 64ms. this equates to an aver- age refresh rate of 15.625s (128mb) or 7.8125s (256mb). however, an auto refresh command must be asserted at least once every 140.6s (128mb) or 70.3s (256mb); burst refreshing or posting by the dram controller greater than eight refresh cycles is not allowed. 22. the valid data window is derived by achieving other specifications: t hp ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. figure 7, derating data valid window t qh - t (dqsq), shows derating curves for duty cycles ranging between 50/50 and 45/55. 23. each byte lane has a corresponding dqs. 24. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period ( t rfc [min]) else cke is low (i.e., during standby). 25. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through to the target ac level, v il (ac) or v ih (ac). b. reach at least the target ac level. c. after the ac target level is reached, continue to maintain at least the target dc level, v il (dc) or v ih (dc). 26. jedec specifies ck and ck# input slew rate must be 1 v/ns (2 v/ns differentially). 27. dq and dm input slew rates must not deviate from dqs by more than 10 percent. if the dq/ dm/dqs slew rate is less than 0.5 v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100 mv/ns reduction in slew rate. if slew rate exceeds 4 v/ns, functionality is uncer- tain. for -6, slew rates must be 0.5 v/ns. 28. v dd must not vary more than 4 percent if cke is not active while any bank is active. 29. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amount. figure 7: derating data valid window t qh - t (dqsq) 3.750 3.700 3.650 3.600 3.550 3.500 3.450 3.400 3.350 3.300 3.250 2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 clock duty cycle ns -75/-75e/-75z @ t ck = 10ns -75/-75e/-75z @ t ck = 7.5ns -6 tbd n/a
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 19 ?2003 micron technology, inc. all rights reserved. 30. t hp min is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck/ inputs, collectively during bank active. 31. reads and writes with auto precharge are not allowed to be issued until t ras (min) can be satis- fied prior to the internal precharge command being issued. 32. any positive glitch to the nominal voltage must be less than 1/3 of the clock and not more than +400mv or 2.9 volts maximum, whichever is less. any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mv or 2.2 volts minimum, whichever is more positive. 33. normal output drive curves: a. the full variation in driver pull-down current from minimum to maximum process, temper- ature and voltage will lie within the outer bounding lines of the v-i curve of figure 8, pull-down characteristics. b. the variation in driver pull-down current within nominal limits of voltage and tempera- ture is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 8, pull-down characteristics. c. the full variation in driver pull-up current from minimum to maximum process, temper- ature and voltage will lie within the outer bounding lines of the v-i curve of figure 9, pull-up characteristics. d. the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 9, pull-up characteristics. e. the full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1v to 1.0v, and at the same voltage and temperature. f. the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source volt- ages from 0.1v to 1.0v. 34. the voltage levels used are derived from a mini- mum v dd level and the referenced test load. in practice, the voltage levels obtained from a prop- erly terminated bus will provide significantly dif- ferent voltage values. 35. v ih overshoot: v ih (max) = v dd + 1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. v il undershoot: v il (min) = -1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 36. this maximum value is derived from the refer- enced test load. in practice, the values obtained in a typical terminated design may reflect up to 310ps less for t hz (max) and the last dvw. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. t lz (min) will prevail over t dqsck (min) + t rpre (max) condition. 37. for slew rates greater than 1v/ns the (lz) transi- tion will start about 310ps earlier. 38. during initialization, v dd , v tt , and v ref must be equal to or less than v dd + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v dd / v dd are 0 volts, provided a minimum of 42 ohms of series resistance is used between the v tt supply and the input pin. 39. the current micron part operates below the slow- est jedec operating frequency of 83 mhz. as such, future die may not reflect this option. figure 8: pull-down characteristics figure 9: pull-up characteristics
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 20 ?2003 micron technology, inc. all rights reserved. 40. for the -6 and -75 i dd 3n is specified to be 35ma per ddr sdram device at 100 mhz. 41. random addressing changing and 50 percent of data changing at every transfer. 42. random addressing changing and 100 percent of data at every transfer. 43. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each rising clock edge, until t ref later. 44. i dd 2n specifies the dq and dqs to be driven to a valid high or low logic level. i dd 2q is similar to i dd 2f except i dd 2q specifies the address and control inputs to remain stable. although i dd 2f, i dd 2n, and i dd 2q are similar, i dd 2f is ?worst case.? 45. whenever the operating frequency is altered, not including jitter, the dll is required to be reset. this is followed by 200 clock cycles. 46. leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 47. when an input signal is high or low, it is defined as a steady state logic high or logic low.
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 21 ?2003 micron technology, inc. all rights reserved. spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (as shown in figure 10, data validity, and figure 11, defi- nition of start and stop). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condi- tion, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indi- cate successful data transfers. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (as shown in fig- ure 12, acknowledge response from receiver). the spd device will always respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write oper- ation have been selected, the spd device will respond with an acknowledge after the receipt of each subse- quent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowl- edge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will termi- nate further data transmissions and await the stop condition to return to standby power mode. figure 10: data validity figure 11: definition of start and stop figure 12: acknowledge response from receiver scl sda data stable data stable data change scl sda start bit stop bit scl from master data output from transmitter data output from receiver 9 8 acknowledge
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 22 ?2003 micron technology, inc. all rights reserved. figure 13: spd eeprom timing diagram table 16: eeprom device select code the most significant bit (b7) is sent first device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 1 0 1 0 sa2 sa1 sa0 rw protection register select code 0 1 1 0 sa2 sa1 sa0 rw table 17: eeprom operating modes mode rw bit wc bytes initial sequence current address read 1v ih or v il 1 start, device select, rw = ?1? random address read 0v ih or v il 1 start, device select, rw = ?0?, address 1v ih or v il 1 restart, device select, rw = ?1? sequential read 1v ih or v il 1 similar to current or random address read byte write 0v il 1 start, device select, rw = ?0? page write 0v il 16 start, device select, rw = ?0? scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 23 ?2003 micron technology, inc. all rights reserved. note: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition, or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a valid stop conditi on of a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to pull-up resistor, and the eeprom does not respond to its slave address. table 18: serial presence-detect eeprom dc operating conditions all voltages referenced to v ss ; v dd = +2.3v to +3.6v parameter/condition symbol min max units supply voltage v dd 2.3 2.7 v input high voltage: logic 1; all inputs v ih v dd 0.7 v dd + 1 v input low voltage: logic 0; all inputs v il -0.3 v dd 0.3 v output low voltage: i out = 3ma v ol ?0.4 v input leakage current: v in = gnd to v dd i li ?2 a output leakage current: v out = gnd to v dd i lo ?2 a power supply current: scl clock frequency = 400 khz i cc 1.0 ma stand-by supply current: vin = v ss or v dd , v dd = 2.5 v i sb ?0.5 a table 19: serial presence-detect eeprom ac operating conditions all voltages referenced to v ss ; v dd = +2.3v to +3.6v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 s data-out hold time t dh 200 ns sda and scl fall time t f 300 ns 2 data-in hold time t hd:dat 0 s start condition hold time t hd:sta 0.6 s clock high period t high 0.6 s noise suppression time constant at scl, sda inputs t i50ns clock low period t low 1.3 s sda and scl rise time t r0.3s2 scl clock frequency f scl 400 khz data-in setup time t su:dat 100 ns start condition setup time t su:sta 0.6 s 3 stop condition setup time t su:sto 0.6 s write cycle time t wrc 10 ms 4
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 24 ?2003 micron technology, inc. all rights reserved. table 20: serial presence-detect matrix ?1?/?0?: serial data, ?driven to high?/?driven to low?; notes appear on page 25 byte description entry (version) mt8vddt3232u mt8vddt6432u 0 number of spd bytes used by micron 128 80 80 1 total number of bytes in spd device 256 08 08 2 fundamental memory type ddr sdram 07 07 3 number of row addresses on assembly 12, 13 0c 0d 4 number of column addresses on assembly 10 0a 0a 5 number of physical ranks on dimm 20202 6 module data width 32 20 20 7 module data width (continued) 00000 8 module voltage interface levels sstl 2.5v 04 04 9 sdram cycle time, ( t ck) (cas latency = 2.5) 6ns (-6) 7.5ns (-75/75e/-75z) 7.5ns (-75) 60 70 75 60 70 75 10 sdram access from clock ( t ac) (cas latency = 2.5) 0.7ns (-6) 0.75ns (-75e/-75z/-75) 70 75 70 75 11 module configuration type none 00 00 12 refresh rate/type 15.62s, 7.8s/self 80 82 13 sdram device width (primary ddr sdram) 80808 14 error-checking ddr sdram data width none 00 00 15 minimum clock delay, back-to-back random column access 1 clock 01 01 16 burst lengths supported 2, 4, 8 0e 0e 17 number of banks on ddr sdram device 40404 18 cas latencies supported 2, 2.5 0c 0c 19 cs latency 00101 20 we latency 10202 21 sdram module attributes unbuffered/diff. clock 20 20 22 sdram device attributes: general fast/concurrent ap c0 c0 23 sdram cycle time, t ck (cas latency = 2) 7.5ns (-6) 10ns (-75e/-75z) 10ns (-75) 75 75 a0 75 75 a0 24 sdram access from clock, t ac (cas latency = 2) 0.7ns (-6) 10ns (-75e/-75z/-75) 70 75 70 75 25 sdram cycle time, t ck (cas latency = 1.5) n/a 00 00 26 sdram access from clock, t ac (cas latency = 1.5) n/a 00 00 27 minimum row precharge time, t rp 18ns (-6) 20ns (-75e) 20ns (-75z/-75) 48 3c 50 48 3c 50 28 minimum row active to row active, t rrd 12ns (-6) 15ns (-75e/-75z/-75) 30 3c 30 3c 29 minimum ras# to cas# delay, t rcd 18ns (-6) 20ns (75e) 20ns (-75z/-75) 48 3c 50 48 3c 50 30 minimum ras# pulse width, t ras (see note 1) 42ns (-6) 45ns (-75e/-75z/-75) 2a 2d 2a 2d 31 module rank density 64mb, 128mb 10 20
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 25 ?2003 micron technology, inc. all rights reserved. note: 1. the value of t ras used for -75 modules is calculated from t rc - t rp. actual device spec. value is 40 ns. 2. the jedec spd specification allows fast or slow slew rate va lues for these bytes. the worst-case (slow slew rate) value is represented here. systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met. 32 address and command setup time, t is (see note 2) 0.8ns (-6) 1.0ns (-75e/-75z/-75) 80 a0 80 a0 33 address and command hold time, t ih (see note 2) 0.8ns (-6) 1.0ns (-75e/-75z/-75) 80 a0 80 a0 34 data/data mask input setup time, t ds 0.45ns (-6) 0.5ns (-75e/-75z/-75) 45 50 45 50 35 data/data mask input hold time, t dh 0.45ns (-6) 0.5ns (-75e/-75z/-75) 45 50 45 50 36-40 reserved 00 00 41 min active auto refresh time t rc 60ns (-6) 65ns (-75e) 65ns (-75z/-75) 3c 3c 41 3c 3c 41 42 minimum auto refresh to active/auto refresh command period, t rfc 72ns (-6) 75ns (-75e/-75z/-75) 48 4b 48 4b 43 sdram device max cycle time, t ck max 12ns (-6) 13ns (-75e/-75z/-75) 30 34 30 34 44 sdram device max dqs-dq skew time, t dqsq 0.45ns (-6) 0.5ns (-75e/-75z) 0.5ns (-75) 2d 32 3c 2d 32 3c 45 sdram device max read data hold skew factor, t qhs 0.55ns (-6) 0.75ns (-75e/-75z/-75) 55 75 55 75 46 reserved 00 00 47 dimm height 01 01 48?61 reserved 00 00 62 spd revision release 1.0 10 10 63 checksum for bytes 0?62 -6 -75e -75z -75 c5 68 95 d5 d8 7b a8 e8 64 manufacturer?s jedec id code micron 2c 2c 65-71 manufacturer?s jedec id code (continued) ff ff 72 manufacturing location 01?12 01?0c 01?0c 73-90 module part number (ascii) variable data variable data 91 pcb identification code 1-9 01-09 01-09 92 identification code (continued) 00000 93 year of manufacturein bcd variable data variable data 94 week of manufacture in bcd variable data variable data 95-98 module serial number variable data variable data 99-127 manufacturer-specific data (rsvd) ?? table 20: serial presence-detect matrix (continued) ?1?/?0?: serial data, ?driven to high?/?driven to low?; notes appear on page 25 byte description entry (version) mt8vddt3232u mt8vddt6432u
128mb, 256mb (x32, dr) 100-pin ddr dimm 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64x32ug_d.fm - rev. d 9/03 en 26 ?2003 micron technology, inc. all rights reserved. ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.m icron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. all other trademarks are the property of their respective owners. figure 14: 100-pin dimm dimensions note: all dimensions are in inches (mil limeters); or typical where noted. data sheet designation released (no mark): this data sheet contains mini- mum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifica- tions are subject to change, as further product devel- opment and data characterization sometimes occur. u1 u2 u3 u4 u5 u6 u7 u8 u9 0.157 (4.0) max pin 1 3.556 (90.32) 3.544 (90.02) 0.70 (17.78) typ 0.118 (3.0) dia (2x) 0.050 (1.27) typ 0.039 (1.0) typ 0.079 (2.00) r (2x) pin 50 pin 100 pin 51 front view 2.850 (72.39) 0.118 (3.0) 0.054 (1.37) 0.046 (1.17) typ 0.039 (1.0) r (2x) 0.118 (3.0) back view 1.206 (30.63) 1.194 (30.33) max min

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